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modelsim simulation time cycles appear to be different than test_bench
i have a testbench which states at the top:
'timescale 1 ns/ 1 ps
a clock which is defined as:
code in testbench
always begin
#5 sys_clk = ~sys_clk;
#20 clk_in = ~clk_in;
#8 clk_acq = ~clk_a...
Dan
Votes: 0
Answers: 1
Missing connection for port 'v1'
I'm working on a systemVerilog code, where a lookup value is being compared to 8 registers of the same bit size, it should give valid 1 if one of the registers matches the the lookup val. everything c...
user18676558
Votes: 0
Answers: 1
Component instance binding in configuration ignored
I have a testbench that should run with the appropriate simulation model for the target device (or a generic behavioural model), so I'm trying to use a configuration to map the component instance to t...
Simon Richter
Votes: 0
Answers: 2
I think it is a bug. ModelSim cannot be called from Quartus on Ubuntu
I have Quartus Prime Lite 21.1 installed on Ubuntu 20.04 and it is working fine.
I also have ModelSim 20.1.1 and it is working fine
I've put the right path to ModelSim on Quartus Prime, and it can ...
domvito55
Votes: 0
Answers: 2