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Questions - fpga

How to calculate a memory of a specific size

I would like to design a 4kb memory. The size of a memory is equal to 2^m words or 2^m*n bits, m for address lines n for data lines. In verilog we can write reg [WordSize-1:0] Mem [0:Address_width]; ...
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B. George

verilog

hardware

fpga

Votes: 0

Answers: 1

Latest Answer

I think better names are WIDTH and DEPTH, as this will better define the memory. So your declaration would be: reg [WIDTH-1:0] Mem [0:DEPTH-1]; This gives you a memory that is WIDTH x DEPTH. Most oft...
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Russell

modelsim simulation time cycles appear to be different than test_bench

i have a testbench which states at the top: 'timescale 1 ns/ 1 ps a clock which is defined as: code in testbench always begin #5 sys_clk = ~sys_clk; #20 clk_in = ~clk_in; #8 clk_acq = ~clk_a...
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Dan

verilog

simulation

fpga

hdl

modelsim

Votes: 0

Answers: 1

Latest Answer

You should have put all the code in text form. You generate clocks following this scheme: always begin #5 sys_clk = ~sys_clk; #20 clk_in = ~clk_in; #8 clk_acq = ~clk_asq; end So, your clocks...
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Serge

Can bazel package depend on a source file in another package

A few years ago I wrote a set of wrappers for Bazel that enabled me to use it to build FPGA code. The FPGA bit is only relevant because the full clean build takes many CPU days so I really care about ...
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Fenster34

bazel

fpga

buck

pants

please.build

Votes: 0

Answers: 1

Latest Answer

The Bazel rules for most languages support doing something like this already. For example, the Python rules bundle source files from multiple packages together, and the C++ rules manage include files ...
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Brian Silverman

Machine state does not change output

As you can see in the code below, I have a machine state with a state called start. This state should take the value of coord_x_reg , increment it by one and assign it to the output port using the ass...
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Ginés Díaz

verilog

fpga

xilinx

xilinx-ise

Votes: 0

Answers: 1

Latest Answer

By investigating, I came to the conclusion that the sensibility list was giving problems. I modified the code so the machine state is inside the always @(posedge CLK, posedge RST). Now works as expect...
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