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how can i make a testbech of the basic VHDL code?
I'm a beginner to VHDL, and I've encountered the following code
process
variable F: integer:=1; variable A: integer:=0;
begin
wait on E;
A :=1;
F :=A+5;
B <= F + 1 after 5ns;
C <= B + ...
Js Park
Votes: 0
Answers: 1
VHDL - Adding/Removing Pipeline Register with Generics
Let's assume I have two processes PROC_A and PROC_B, and they share a signal between them. Let me write a dummy example:
library ieee;
use ieee.std_logic_1164.all;
entity example is
port (
c...
efe373
Votes: 0
Answers: 3
VHDL - AND variable number of bits
I have a w*y-bit width std_logic_vector named matrix where w and y are integers. I want to have y-bit width std_logic_vector called output that its bits are concurrently assigned to AND of w bits of m...
efe373
Votes: 0
Answers: 2
Is there a way to rename std_logic_vector to a shorter name like 'v'?
Personally, I get sick of typing std_logic_vector in VHDL code... it's too long... how can I alias the type name 'std_logic_vector' to a shorter name like 'v' for vector:
library ieee;
use ieee.std_lo...
pico
Votes: 0
Answers: 2