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modelsim simulation time cycles appear to be different than test_bench
i have a testbench which states at the top:
'timescale 1 ns/ 1 ps
a clock which is defined as:
code in testbench
always begin
#5 sys_clk = ~sys_clk;
#20 clk_in = ~clk_in;
#8 clk_acq = ~clk_a...
Dan
Votes: 0
Answers: 1
Implementing a 16 bit register in Nand2Tetris (HDL code)
think I am most of the way there, and my hardware simulator accepts the chip, but when running the test script the comparison fails half way through, I'm guessing there is an issue with feeding the ou...
Tropicalthunder27
Votes: 0
Answers: 2
Best way to optionally register inputs
I have a systemverilog module with a LOT of input signals of varying sizes. I want to optionally register them before use. Here is my desired criteria for the code that does this optional registering:...
Ryan Johnson
Votes: 0
Answers: 1
Chapter 2 ALU.hdl not working on final line
When I run ALU-nostat.tst, the code executes perfectly. However, when I run ALU.tst, the code stops on line 1. If I then click the forward arrow again and allow it to test out the following test cases...
CuriousCoder
Votes: 0
Answers: 1