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Questions about xilinx-ise

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Questions - xilinx-ise

Machine state does not change output

As you can see in the code below, I have a machine state with a state called start. This state should take the value of coord_x_reg , increment it by one and assign it to the output port using the ass...
test-img

Ginés Díaz

verilog

fpga

xilinx

xilinx-ise

Votes: 0

Answers: 1

Latest Answer

By investigating, I came to the conclusion that the sensibility list was giving problems. I modified the code so the machine state is inside the always @(posedge CLK, posedge RST). Now works as expect...
test-img

Ginés Díaz

How to properly instantiate a module and pass registers to it

[![Simulation: modules seem to be running but not passing/recieving appropriate info?][1]][1] I'm trying to become familiar with the Xilinx iSim utility. I am comfortable simulating a single, self con...
test-img

Tesla047

verilog

xilinx-ise

Votes: 0

Answers: 1

Latest Answer

You connected the wrong signal to the BCD_sevseg instance in the testbench module mod_10_II_sim. In the testbench, you only toggle the clk signal, but not the clock signal. Change: BCD_sevseg inst_on...
test-img

toolic

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