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Questions - digital-logic

VHDL - Upper digit output does not go up from '0000', when implementing two-digit-bcd-counter

I'm trying to implement two-digit-bcd-counter in VHDL, by referring to this diagram: This is my code for it: library ieee; use ieee.std_logic_1164.all; entity two_digit_bcd_counter is port( v_cc...
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theCursedPirate

vhdl

fpga

digital-logic

hardware

Votes: 0

Answers: 1

Latest Answer

y3 is going to clear itself, through y8 in an asyncnhronous way. This design is generating a glitch on y3 longh enough to self reset, but it will never be sampled on bcd_counter_1
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G. C.

Output not as expected when implementing 4-bit SISO register in VHDL

I am trying to create a 4-bit SISO register in VHDL, and this is my main code: library ieee; use ieee.std_logic_1164.all; entity right_shift_siso_reg_4 is port( D_in : in std_logic; clk : ...
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theCursedPirate

vhdl

fpga

digital-logic

hardware

Votes: 0

Answers: 2

Latest Answer

Your design doesn't look like having any problem. I wrote a testbench and tried it out myself. Here is the testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity testbe...
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Caglayan DOKME

Problem while implementing JK-Flip Flop in VHDL

I'm trying to implement JK flip-flop in VHDL, and here is my code: library ieee; use ieee.std_logic_1164.all; entity jk_flip_flop is port( J, K : in std_logic; clk : in std_logic; ...
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theCursedPirate

vhdl

digital-logic

hardware

digital-design

Votes: 0

Answers: 1

Latest Answer

So your temp := value when ... else ... statement only works outside of a process statement. So you've got three options. Option 1 Upgrade to VHDL 2008, where you can also use this kind of statement i...
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Bill Lynch

How to represent multiple-output logic circuits in tree-based genetic programming

Consider the following digital logic circuit, which has multiple inputs and one output: The logic circuit above can be represented in tree form: This tree representation could then be used in a tree...
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Flux

tree

logic

genetic-programming

digital-logic

s-expression

Votes: 0

Answers: 1

Latest Answer

I worked in a similar problem in a different field, but I think you could have a quite straightforward solution by instead of using a binary tree using a tree represented by list of lists. For instanc...
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Javiagu13

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