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Questions - digital-design

Verilog code is compiled but there is no "vcdplus.vpd" waveform file being created when using "$vcdpluson" - FSM Sequence Dectector

My verilog code for my Finite State Machine - Moore (Non-Overlapping) - Sequence detector is not generating a "vcdplus.vpd" waveform file after I have compiled. I'm compiling my verilog code...
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harhote

verilog

state-machine

digital-design

Votes: 0

Answers: 1

Latest Answer

The code you provided cannot be compiled at all. It contains two errors: the forever statement in the fsm_moore_tb module is outside of any procedural block, which is illegal. initial forever #5 clo...
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Serge

Problem while implementing JK-Flip Flop in VHDL

I'm trying to implement JK flip-flop in VHDL, and here is my code: library ieee; use ieee.std_logic_1164.all; entity jk_flip_flop is port( J, K : in std_logic; clk : in std_logic; ...
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theCursedPirate

vhdl

digital-logic

hardware

digital-design

Votes: 0

Answers: 1

Latest Answer

So your temp := value when ... else ... statement only works outside of a process statement. So you've got three options. Option 1 Upgrade to VHDL 2008, where you can also use this kind of statement i...
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Bill Lynch

Programmable Logic Array (PLA) Design

I need to design Programmable Logic Array (PLA) circuit with given functions. How can I design circuit with POS form functions. Can someone explain that? enter image description here
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hakan-eryaz

logic

digital-design

Votes: 0

Answers: 1

Latest Answer

Below is the design process completed for F, the other two outputs, G and H, can done in a similar fashon. F Truth Table A B C D # F G H 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1...
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Andrew

How to create K-MAP from function

How can I create a K-MAP by looking at this function.I dont know how to create one
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Emirhan Selim Uzun

digital-logic

digital-design

Votes: 0

Answers: 1

Latest Answer

Create the truth table, from that create the K-MAPs (Karnaugh maps), from that create the booleans, from that create the CKTs. One of the 6 outputs, Y5 (Y=f(x)), is completed below ... Tru...
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Andrew

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