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How to access XDMA BAR0 in Petalinux?
I have a block design and hardware configuration with a Zynq processor running Petalinux. I furthermore have an XDMA IP configured as a memory-mapped endpoint. I have configured BAR0 and BAR2 in the P...
Hedam
Votes: 0
Answers: 1
why there is a overlapped output at putty while calling a function is written using xuartps.h to send data to uart in normal mode in zynq?
I am trying to send data from zynq soc 7000 board to pc using uart through a function (driver xuartps.h). within the main program, the code works but calling it from function, output at putty gets ove...
Roy
Votes: 0
Answers: 1
vivado HLS or SDsoc for use openCV
I want to do an image processing by openCV on FPGA . But I do not know if I should use the SDsoc method or the vivadoHLS method. The size of the images I am going to process is large and I want to sol...
tom
Votes: 0
Answers: 1
How to store image in the FPGA for real time video processing?
I am implementing a video processing project in real time which comes from an HDMI input. The video input is going to have a green background, which will be replaced by an image stored in the FPGA in ...
Florence
Votes: 0
Answers: 0