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Questions - zynq-ultrascale+

How to access XDMA BAR0 in Petalinux?

I have a block design and hardware configuration with a Zynq processor running Petalinux. I furthermore have an XDMA IP configured as a memory-mapped endpoint. I have configured BAR0 and BAR2 in the P...
test-img

Hedam

xilinx

dma

zynq

petalinux

zynq-ultrascale+

Votes: 0

Answers: 1

Latest Answer

When you export the .xsa file you will have the BAR0 address defined in the register space of your PS. Furthermore you can decompile the device tree to check that the xilinx-xdma IP has the correct BA...
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Fra93

Why are the headers not found in the Xilinx SDK?

I am following the course "Introduction to Deep Learning with Xilinx SoCs Technical Training Course" for the Ultra96v2 board and reached Lab No. 5. I am able to follow along until I am suppo...
test-img

Vandrey

c++

linux

eclipse-cdt

xilinx

zynq-ultrascale+

Votes: 0

Answers: 0

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