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Questions - test-bench

Why is the direction in port mappings from the design to the test-bench and not vice versa?

When testing with a testbench in VHDL we map the I/O from the design we are testing to the I/O of the test bench. For me, it would make sense to give the input of our design some generated values from...
test-img

stht55

testing

vhdl

test-bench

Votes: 0

Answers: 1

Latest Answer

Actually you need to stimulate the input of your UUT. Currently your test bench is not complete. Add some sequence to assign different values to tb_input. And then add some checks that tb_output carri...
test-img

the busybee

$fclose placement in testbench

I want to use $fmonitor so that an output value is written to a file every time the value changes. When I place $fclose inside the initial begin block, there are no errors. However, unsurprisingly, th...
test-img

Rahel Miz

verilog

test-bench

Votes: 0

Answers: 3

Latest Answer

$fclose must be used inside a procedural block, like an initial block. That is why you get the syntax error when you place it right before endmodule. If you want the file to be written until the end ...
test-img

toolic

How to use only one DUT for different test cases in a VHDL testbench and how to detect SPI master's mode on the slave side?

First I would like to mention that I'm still new to the VHDL World so please bear with me. Currently, I'm working on an SPI project where I created a generic master module that can send and receive di...
test-img

Amr

vhdl

fpga

spi

master-slave

test-bench

Votes: 0

Answers: 1

Latest Answer

Have you written a test plan for your SPI project? How many test cases are required to test a single data width of your SPI project? Once you determine that, you can decide how to solve the problem...
test-img

Jim Lewis

No response from uut in testbench

I am not getting any response from the uut in the testbench. The module exp2_up_down_counter works ok without testbench, but gives output as xxxx when instantiated in the testbench. Here is the main m...
test-img

Chaitanya Chhichhia

verilog

verification

hdl

test-bench

Votes: 0

Answers: 1

Latest Answer

In exp2_up_down_counter, count is declared as a reg. This means that its default value is X at time 0. Since the reset signal is synchronous to the clock, you need to wait for the 1st posedge of clo...
test-img

toolic

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