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Questions - immediate-operand

What are the common ways instruction decoders deal with using constants over registers in microcontrollers?

Specifically, if the assembly instruction has a constant as one of the operands, how would instruction decoder pass it to the ALU? So far I thought of three ways to do it. Pass the constant into a fr...
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Nikolai Savulkin

assembly

cpu

cpu-architecture

immediate-operand

Votes: 0

Answers: 1

Latest Answer

Pass the constant in the same bus as the address would go and separately trigger some enable 1-bit bus to signify its a constant. What you're describing as a 1-bit indication is called a control sig...
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Erik Eidt

ARMv7 T3 encoding for adds

I can't tell how to determine the following: i, 10th bit on the left. imm3, what's the difference for this one with imm8?
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Mzq

assembly

arm

thumb

immediate-operand

instruction-encoding

Votes: 0

Answers: 1

Latest Answer

The fields i and imm3 apply a transformation to the imm8 constant in order to generate more 32 bit constants. Here is the official documentation which sadly doesn't explain much. There is also a post ...
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Homer512

Replace `movss xmm0, cs:dword_5B27420` with `movss xmm0, immediate`

I have a linux .so file in Ida Pro and I have the following instruction: movss xmm0, cs:dword_5B27420 Is it possible to move a fixed value into xmm0 using the same or less number of bytes than that...
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Alvaro Hernandorena

assembly

x86

reverse-engineering

sse

immediate-operand

Votes: 0

Answers: 1

Latest Answer

Not in fewer bytes; if you don't have room here, you'd have to jump somewhere else and then back, or just change the RIP-relative address to load a different constant from somewhere else. (e.g. from ...
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Peter Cordes

MIPS - SPIM parser immediate value out of range for bitwise ANDI

Was trying to test my program with SPIM and have this message spim: (parser) immediate value (-16) out of range (0 .. 65535) on line 56 of file code1.a andi $t1, $t0, 0xfffffff0 what could be the p...
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avatar

assembly

mips

spim

immediate-operand

Votes: 0

Answers: 1

Latest Answer

The MIPS processor cannot do that operation in one instruction.  The andi instruction is an I-Type instruction, which holds a 16-bit immediate — further the andi instruction zero extends the 16-bit im...
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Erik Eidt

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